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module Schedgen

: sig
#
type code_dag_node = {
# instr
: Linearize.instruction;
# delay
: int;
# mutable sons
: (code_dag_node * int) list;
# mutable date
: int;
# mutable length
: int;
# mutable ancestors
: int;
# mutable emitted_ancestors
: int;
}
#
class virtual scheduler_generic :
#
method virtual oper_issue_cycles : Mach.operation -> int
#
method virtual oper_latency : Mach.operation -> int
#
method reload_retaddr_issue_cycles : int
#
method reload_retaddr_latency : int
#
method oper_in_basic_block : Mach.operation -> bool
#
method is_store : Mach.operation -> bool
#
method is_load : Mach.operation -> bool
#
method is_checkbound : Mach.operation -> bool
#
method schedule_fundecl : Linearize.fundecl -> Linearize.fundecl
#
val reset : unit -> unit
end